The present invention relates to a semiconductor device comprising non-volatile memory cells in a semiconductor substrate, each one of the memory cells comprising, in said substrate, a source region, a drain region and a channel region between said source and drain regions, and comprising, on top of said substrate, a floating gate separated from said channel region by a floating gate insulating layer, a select gate adjacent to said floating gate and separated from said channel region by a select gate insulating layer, and a control gate separated from said floating gate by a control gate insulating layer.
Non-volatile memory (NVM) cells are used in FlashROM and EEPROM applications. Such a semiconductor device comprising NVM cells each containing one transistor, is known from U.S. Pat. No. 5,612,237. In such a 1T NVM cell, a first and a second electrode (known as source and drain) are formed on a p-Si substrate. Between the two electrodes an insulating layer is formed on the p-Si substrate to insulate the channel region between the source and drain regions. On the insulating layer a floating gate is formed. On top of the floating gate structure a control gate is formed to control the transistor.
As is known to persons skilled in the art, in a structure as described above, the floating gate can be electrically charged by electrons from the underlying p-Si, in a process known as hot-electron-injection. Due to the insulation of the floating gate the electrons are trapped in the floating gate.
The potential of the floating gate is controlled by the amount of charge that is trapped on the floating gate, and by the control gate. The presence of a negative electric charge on the floating gate changes the conducting properties of the transistor, which can be used in semiconductor non-volatile memory cells. Circuitry within a semiconductor memory device can determine the logic state (xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d) of the cell.
A disadvantage of the known semiconductor device, however, is that erasure of the cell by emission of the electric charge from the floating gate can result in over-erasure, which charges the floating gate positively, causing bit line leakage if the cell is not charged subsequently, i.e. remains in the low-threshold voltage state.
As is known to those versed in the art, to overcome this problem 2T NVM cells comprising two transistors are applied in semiconductor non-volatile memory devices. A 2T NVM cell consists of a floating gate transistor (as found in a 1T cell) in series with an access transistor. Additional advantages are the relatively low read voltages and the reduced susceptibility to failure during programming, erasure and reading. Such a semiconductor device comprising a 2T NVM cell is known from U.S. Pat. No. 5,041,886, 5,073,513, 5,293,328, 5,583,811 and 5,910,912, as well as from WO99/13513. In the 2T NVM cell known from U.S. Pat. No. 5,910,912, in between source and drain regions, an insulating layer is formed on a p-Si substrate to create a channel region. On this insulating layer two gates, i.e. a select gate and a floating gate, are formed, which are separated by an insulating sidewall. Both gates are covered by an insulating layer. On this structure a control gate is formed, which covers the. complete floating gate and part of the select gate. Both the select gate and the floating gate are formed as sidewall spacers. Thus, the dimensions of the structure formed by the select gate and the floating gate are smaller than the dimensions obtainable with optical lithography. However, the cell size of this 2T NVM cell structure is still limited by lithographic processing. Due to the accuracy of alignment observed in subsequent lithographic steps to form the control gate on top of the floating gate and, partly, on top of the select gate, an overlap of the structures is required, and some additional oversizing of structures is usually allowed for. Due to this consideration, and since the smallest dimension of the control gate is determined by feature size F, the cell size will be larger than the feature size F, which is defined here as the smallest size that can be transferred by lithography (for a given technology level and a given generation of semiconductor devices).
In U.S. Pat. No. 6,011,725, a non-volatile EEPROM is disclosed that is able to store two bits of information in a non-conducting charge trapping dielectric layer, e.g. silicon nitride, in between two silicon dioxide layers.
It is an object of the present invention to provide a semiconductor device comprising a semiconductor non-volatile memory device of the EEPROM or FlashROM type, in which the memory cell comprises at least one bit and the cell size, in a preferred embodiment, can be reduced to a surface area of 1F2.
In a first preferred embodiment, the present invention relates to a semiconductor device comprising a non-volatile memory cell, for storing at least one bit, in a semiconductor substrate comprising, in the substrate, a source region, a drain region and a channel region between the source and drain regions, and comprising, on top of the substrate, a floating gate separated from the channel region by a floating gate insulating layer, a select gate adjacent to the floating gate and separated from the channel region by a select gate insulating layer, and a control gate separated from the floating gate by a control gate insulating layer, wherein the control gate is produced as a sidewall spacer and the floating gate is a non-conducting charge trapping dielectric layer.
In this embodiment,and in further embodiments, the non-conducting charge trapping dielectric layer consists of a silicon nitride layer.
Furthermore, in this first embodiment, the present invention relates to a semiconductor device comprising at least two adjacent non-volatile memory cells, as defined above, which at least two adjacent memory cells are arranged in a virtual ground arrangement.
In such a semiconductor device, the area of a non-volatile memory cell that can be allotted to one bit equals a surface area of 4 F2, where F is defined as the smallest size that can be transferred by lithography.
In a second preferred embodiment, the present invention relates to a semiconductor device, as defined above, comprising at least first and second subsets of nonvolatile memory cells as defined above, wherein the first subset comprises two adjacent memory cells sharing a first select gate line extending in a first direction, and the second subset comprises two further adjacent memory cells arranged next to the first subset in a second direction perpendicular to the first direction and sharing a second select gate line extending in the first direction, the first and second gate lines being separated by a thin insulating layer.
Moreover, in the second preferred embodiment, the present invention also relates to a semiconductor device, wherein the memory cells of the first subset are arranged in a virtual ground arrangement, and the memory cells of the second subset are also arranged in a virtual ground arrangement.
In such a semiconductor device, the area of a non-volatile memory cell that can be allotted to one bit equals a surface area of 2 F2.
In a third preferred embodiment, the present invention relates to a semiconductor device comprising a memory cell, as defined above with respect to the first embodiment, which, for storing a second bit, comprises, on top of the substrate, a further floating gate separated from the channel region by a further floating gate insulating layer, and a further control gate separated from the further floating gate by a further control gate insulating layer, wherein the further control gate is produced so as to be a sidewall spacer and the further floating gate is a further non-conducting charge trapping dielectric layer.
Moreover, in this third embodiment, the present invention also relates to a semiconductor device comprising at least two adjacent non-volatile memory cells, as defined above with respect to this embodiment, wherein the at least two adjacent memory cells are arranged in a virtual ground arrangement.
In such a semiconductor device, the area of a non-volatile memory cell that can be allotted to one bit equals a surface area of 2 F2.
In a fourth embodiment, the present invention relates to a semiconductor device as defined in the third embodiment, comprising at least first and second subsets of non-volatile memory cells as defined in the third embodiment, wherein the first subset comprises two adjacent memory cells sharing a first select gate line extending in a first direction, and the second subset comprises two further adjacent memory cells arranged next to the first subset in a second direction perpendicular to the first direction and sharing a second select gate line extending in the first direction, the first and second gate lines being separated by a thin insulating layer.
Furthermore, in the fourth embodiment, the present invention relates to a semiconductor device, wherein the memory cells of the first subset are arranged in a virtual ground arrangement, and the memory cells of the second subset are also arranged in a virtual ground arrangement.
In such a semiconductor device, the area of a non-volatile memory cell that can be allotted to one bit equals a surface area of 1 F2.